ISO7816 3.2.a - Connection and activation of the contacts
The electrical circuits shall not be activated until the contacts are connected to the interface device so as to
avoid possible damage to any card meeting these standards.
The activation of the contacts by the interface device shall consist of the consecutive operations:
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- RST is in state L;
- VCC shall be powered;
- I/O in the interface device shall be put in reception mode;
- VPP shall be raised to idle state;
- CLK shallbe provided with a suitable and stable clock.
ISO7816 3.2.b - Reset of the card
A card reset is initiated by the interface device, whereupon the card shall respond with an Answer to Reset as
describe in 2.4.
By the end of the activation of the contacts (RST is in L, VCC powered and stable, I/O in reception mode in the
interface device, VPP stable at idle level, CLK provided with a suitable and stable clock), the card answering
asynchronously is ready for reset.
The clock signal is applied to CLK at time T0. The I/O line shall be set to state Z within 200 clcok cycles of the
clock signal (t2) being applied to CLK (time t2 after T0).
An internally reset card reset after a few cycles of clock signal. The Answer to Reset on I/O shall begin between
400 and 40 000 clock cycles (t1) after the clock signal is applied to CLK (time t1 after T0).
A card with an active low reset is reset by maintaining RST in state L for at least 40 000 clock cycles (t3) after
the clock signal is applied on CLK (time t3 after T0). Thus if no Answer to Reset begind within 40 000 clock
cycles (t3) with RST in state L, RST is put to state H (at time T1). The
Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the rising edge of the signal
on RST (time t1 after T1).
If the Anwser to Reset does not begin within 40 000 clock cycles (t3) with RST in state H (t3 after T1), the
signal on RST shall be returned to state L (at time T2) and the contacts shall be desactivated by the interface
device.
GND ________________________________________________________________________
__________________________________________________________________
VCC _| : :|___
:_______________________________________________________________:
VPP __|: |____
: t3 t3 :
:<--------------------------->:<------------------------------->:
: :_________________________________:
RST ___:_____________________________| |____
: : :
CLK ___|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||____
: t1 : :
:<-------------->: : :
: __________:____________:_________________________________:
I/O __XXXXXXXX |____________:_______Answer____________________:XXXX
(IR) : : : :
: t2 : : t1 :
:<---->: :<---------->: :
: _______________________:_________________________________:
I/O __XXXXXXXX : |______Answer________:XXXX
(AL) : t2 : : :
:<---->: : :
: :_________________________________:
I/O __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX: :XXXXX
(SH) : : :
T0 T1 T2
IR : Internal Reset t2 <= 200/fi
AL : Asynchronous Reset 400/fi <= t1 <= 40000/fi
SH : Syncronous Reset 40000/fi <= t3
Figure1 : Reset of the card
With a card answering synchonously, the interface device sets all the lines to state L (See figure 2). VCC is the
powered, VPP is set to idle state, CLK and RST remain in L state, I/O is put in reception mode in the interface
device, RST shall be maintained in state H for at least 50 us (t12), before returning to state L again.
The clock pulse is applied after an interval (t10) from the rising edge of the reset signal. The duration of the
state H of the clock pulse can be any value between 10 us and 50 us ; no more than one clock pulse during
reset high is allowed. The time interval between the falling edges on CLK
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and RST is t11.
The first data bit is obtained as an answer to reset on I/O while CLK is in state L and is valid after an interval t13
from the falling edge on RST.
______________________________________________________________________
VCC__/
_____________________________________________________________________
VPP___/
t12
:<---------------->:
:__________________:
RST_____/: \_______________________________________________
: :
: t10 t11 : t15 t16
:<---->: :<---->: t14 :<---->: :<---->:
: ____ : :<---->: :______: : : _______
CLK_____________:/ 1 \:______:______:/ 2 \:______:/ 3 \_______
: :
: t13 : t17
:<---->: :<---->:
_____________________________ :______________ :______________ ___
I/O___//////////////////////////////\:_______1______X-X_______2_______X-X___
5us <= t10 10us <= t14 <= 100us Clock low after RST
5us <= t11 10us <= t15 <= 50us Clock High
50us <= t12 ........ Reset High 10us <= t16 <= 100us Clock Low
t13 <= 10us Propagation delay t17 <= 10us Propagation delay
Figure2 : Reset of the card when a synchronous answer is expected.
NOTES:
1 - The internal state of the card is assumed not to be defined before reset. Therefore the design of the card has
to avoid inproper operation.
2 - In order to continue the dialogue with the card, RST shall be maintained in the state where an answer occurs
on I/O.
3 - Reset of a card can be initiated by the interface device at its discetion at any time.
4 - Interface devices may support one or more of these types of reset behaviour. The priority of testing for
asynchronous or synchronous cards is not defined in this standard.
ISO7816 3.2.c - Deactivation of the contacts
When informations exchange is terminated or aborted (unresponsive card or detection of card removal), the
electrical contacts shall be desactivated.
The deactivation by the interface device shall consist of the consecutive operations:
- State L on RST;
- State L on CLK;
- Vpp inactive;
- State A on I/O;
- VCC inactive;
ISO7816 3.3 Answer to Reset
Two types of transmissions are considered:
* Asynchronous transmission:
In this type of transmission, characters are transmitted on the I/O line in an asynchronous half duplex mode.
Each character includes an 8bit byte.
* Synchronous transmission:
In this type of transmission, a series of bits is transmitted on the I/O line in half duplex mode in synchronisation
with the clock signal on CLK.
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ISO7816 3.1.a - Answer to Reset in asynchronous transmission
* Bit duration
""""""""""""
The nominal bit duration used on I/O is defined as one Elementary Time Unit (etu).
For cards having internal clock, the initial etu is 1/9600 s.
For cards using the external clock, there is a linear relationship between the Elementary Time Unit used on I/O
and the period provided by the interface device on CLK.
The initial etu is 372/fi s where fi is in Hertz.
The initial frequency fi is provided by the interface device on CLK during the Answer to Reset.
In order to read the initial character (TS), all cards shall initially be operated with fi in the range of 1 MHz to 5
MHz.
* Character frame during answer to reset
""""""""""""""""""""""""""""""""""""""
Prior to the transmission of a character, I/O shall be in state Z.
A character consists of ten consecutive bits:
- a start bit in state A;
- eight bits of information, designated ba to bh and conveying a data byte;
- a tenth bit bi used for even parity checking.
A data byte consists of 8 bits designated b1 to b8, from the least significant bit (lsb, b1) to the most significant
bit (msb, b8).
Conventions (level coding, connecting levels Z/A to digits 1 or 0: and a bit significance, connecting ba...bh to
b1...b8) are specified in the initial character, call TS, which is transmitted by the card in response to reset.
Parity is correct when the number of ONES is even in the sequence from ba to bi.
Whithin a character, the time from the leading edge of the start bit to the trailing edge of the nth bit shall equal
(n+/-0.2) etu.
When searching for a start, the receiver samples I/O periodically. The time origin being the mean between last
observation of level Z and first observation of level A, the start shall be verified before 0.7 etu, and then ba is
received at (1.5 +/-0.2) etu. Parity is checked on the fly.
NOTE : When searching for a start, the sampling time shall be less than 0.2 etu so that all the test zones are
distinct from the transition zones.
The delay between two consecutives characters (between start leading edges) is at least 12 etu, including a
character duration (10+/-0.2) etu plus a guardtime, the interface device and the card reamain both in reception,
so that I/O is in state Z.
Start Parity Next
bit <----- 8 data bits -----> bit Start bit
Z ____ ________________________________......______ __
| | | | | | | | | | | | |
I/O | |ba|bb|bc|bd|be|bf|bg|bh|bi| Guardtime | |
|___|__|__|__|__|__|__|__|__|__| |___|_
A : : : :
0 t1 : t10
: :
:<---- (n+/-0.2) etu --->:
Figure 3: Character frame
During the Answer to Reset, the delay between the start leading edges of two consecutives characters from the
card shall not exeed 9600 etu. This maximum is named initial waiting time.
* Error detection and character repetition
""""""""""""""""""""""""""""""""""""""""
During the answer to reset, the following characters repetition procedure depends on the protocol type. This
procedure is mandatory for cards using the protocol type T=0; it is optional for the interface device and for the
other cards.
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The transmitter tests I/O (11+/-0.2) etu after the start leading edge:
- If I/O is in state Z, the correct reception is assumed.
- If I/O is in state A, the transmission is assumed to have been incorrect. The disputed character shall be
repeated after a delay of at least 2 etu after detection of the error signal.
When parity is incorrect, from (10.5+/-0.2) etu, the receiver transmits an error signal at state A for 1 etu
minimum and 2 etu maximum. The receiver then shall expect a repetition of the disputed character (see figure
8).
If no character repetition is provided by the card, - The card ignores and shall not suffer damage from the error
signal coming from the interface device.
- The interface device shall be able to initiate the reception and the whole Answer to Reset response sequence.
* Structures and content
""""""""""""""""""""""
A reset operation results in the answer from the card consisting of the initial character TS followed by at most
32 characters in the following order:
- T0 ................... Format character (Mandatory)
- TAi, TBi, TCi, TDi ... Interface characters (Optional)
- T1, T2, ... ,TK ...... Historical characters (Optional)
- TCK .................. Check character (Conditional)
Reset
|
| _________________________________________ _______ _________
| | | | | | | | | | | | | | | | |
'-->| TS| T0|TA1|TB1|TC1|TD1|TA2|TB2|TC2|TD2| ......... | T1| ... | TK|TCK|
|___|___|___|___|___|___|___|___|___|___|_ _|___|_ _|__ |___|
TS : Initial character
TO : Format character
TAi : Interface character [ codes FI,DI ]
TBi : Interface character [ codes II,PI1 ]
TCi : Interface character [ codes N ]
TDi : Interface character [ codes Yi+1, T ]
T1, ... , TK : Historical characters (max,15)
TCK : Check character
Figure 4 : General configuration of the Answer to Reset
The interface characters specify physical parameters of the integrated circuit in the card and logical
characteristics of the subsequent exchange protocol.
The historical characters designate general information, for example, the card manufacturer, the chip inserted in
the card, the masked ROM in the chip, the state of the life of the card. The specification of the historical
characters falls outside the scope of this part of ISO/IEC7816.
For national simplicity, T0, TAi, ... ,TCK will designate the bytes as well as the characters in which they are
contained.
Structure of TS, the initial character
--------------------------------------
The initial character TS provides a bit shynchronisation sequence and defines the conventions to code data bytes
in all subsequent characters. These conventions refer to ISO1177.
I/O is initially in state Z. A bit synchronisation sequence (Z)AZZA is defined for the start bit and bits ba bb bc
(see figure 5).
The last 3 bits bg bh bi shall be AAZ for checking parity.
NOTE : This allows the interface device to determinate the etu initially used by the card. An alternate
measurement of etu is a third of the delay between the first two falling edges in TS. Transmission and reception
mechanisms in the card shall be consistent with the alternate
definition of etu.
The two possible values of TS (ten consecutive bits from start to bi and corresponding hexadecimal value) are
- Inverse convention : (Z)ZZAAAAAZ
where logic level ONE is A, ba is b8 (msb is first), equal to $3F when decoded by inverse convention.
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- Direct convention : (Z)ZZAZZZAAZ
where logic level ONE is Z, ba is b1 (lsb first), equal to $3B when decoded by direct convention.
Start ba bb bc bd be bf bg bh bi
Z ____ _______ ___________ ______
| | | | | Z Z Z | | | |
(Z)| A | Z Z | A | or | | Z (Z)
A |___| |___|_A___A___A_|___|___|
Figure 5 : Initial character TS
--------
Structure of the subsequent characters in the Answer to Reset
-------------------------------------------------------------
The initial character TS is followed by a variable number of subsequent characters in the following order: The
format character T0 and, optionally the interface characters TAi, TBi, TCi, TDi and the
historical characters T1, T2, ... , TK and conditionally, the check character TCK.
The presence of the interface characters is indicated by a bit map technique explained below.
The presence of the historical characters is indicated by the number of bytes as specified in the format character
defined below.
The presence of the check character TCK depends on the protocol type(s) as defined as below.
- Format character T0
-------------------
The T0 character contains two parts:
- The most significant half byte (b5, b6, b7, b8) is named Y1 and indicates with a logic level ONE the presence
of subsequent characters TA1, TB1, TC1, TD1 respectively.
- The least significant half byte (b4 to b1) is named K and indicates the number (0 to 15) of historical
characters.
,----,----,----,----,----,----,----,----,
| b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
'----'----'----'----'----'----'----'----'
:<------- Y1 ------>:<-------- K ------>:
Y1 : indicator for the presence of the interface characters
TA1 is transmitted when b5=1
TB1 is transmitted when b6=1
TC1 is transmitted when b7=1
TD1 is transmitted when b8=1
K : number of hitorical characters
Figure 6 : Informations provided by T0
--------
- Interface characters TAi, TBi, TCi, TDi
---------------------------------------
TAi, TBi, TCi (i=1, 2, 3, ... ) indicate the protocol parameters.
TDi indicates the protocol type T and the presence of subsequent
characters.
Bits b5, b6, b7, b8 of the byte containing Yi (T0 contains Y1; TDi contains Yi+1) state whelther character TAi for
b5, character TBi for b6, character TCi for b7, character TDi for b8 are or are not (depending on whether the
relevant bit is 1 or 0) transmitted subsequently in this
order after the character containing Yi.
When needed, the interface device shall attribute a default value to information corresponding to a non
transmitted interface character.
When TDi is not transmitted, the default value of Yi+1 is null, indicating that no further interface characters
TAi+j, TBi+j, TCi+j, TDi+j will be transmitted.
,----,----,----,----,----,----,----,----,
| b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
'----'----'----'----'----'----'----'----'
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:<------ Yi+1 ----->:<------- T ------->:
Yi+1 : indicator for the presence of the interface characters
TAi+1 is transmitted when b5=1
TBi+1 is transmitted when b6=1
TCi+1 is transmitted when b7=1
TDi+1 is transmitted when b8=1
T : Protocol type for subsequent transmission.
Figure 7 : Informations provided by TDi
--------
- Historical characters T1, T2, ... ,TK
-------------------------------------
When K is not null, the answer to reset is continued by transmitting K historical characters T1, T2, ... , TK.
- Check character TCK
-------------------
The value of TCK shall be such that the exclusive-oring of all bytes from T0 to TCK included is null.
The answer to reset is complete 12 etu after the leading edge of the last character.
Protocol type T
---------------
The four least significant bits of any interface character TDi indicate a protocol type T, specifying rules to be
used to process transmission protocols. When TDi is not transmitted, T=0 is used.
T=0 is the asynchronous half duplex character transmission protocol.
T=1 is the asynchronous half duplex block transmission protocol.
T=2 and T=3 are reserved for future full duplex operations.
T=4 is reserved for an enhanced asynchronous half duplex character
transmission protocol.
T=5 to T=13 are reserved for future use.
T=14 is reserved for protocols standardized by ISO.
T=15 is reserved for future extension.
NOTE : If only T=0 is indicated, TCK shall not be sent. In all other cases TCK shall be sent.
Specifications of the global interface bytes
--------------------------------------------
Among the interface bytes possibly transmitted by the card in answering to reset, this subclaus defines only the
global interface bytes TA1,TB1, TC1, TD1.
These global interface bytes convey information to determine parameters which the interface device shall take
into account.
- Parameters F, D, I, P, N
------------------------
This initial etu is used during answer to reset is replaced by the work etu during subsequent transmission. F is
the clock rate conversion factor and D is the bit rate adjustment factor to determine the work etu in subsequent
transmissions.
For internal clock cards:
initial etu = 1/9600 s work etu = (1/D)*(1/9600) s
For external clock cards:
initial etu = 372/fi s work etu = (1/D)*(F/fs) s
The minimum value of fs shall be 1MHz.
The maximum value of fs is given by table 6.
I and P define the active state at VPP.
- Maximum programming current : Ipp = 1mA
- Programming voltage : Vpp = P.V
N is an extra guardtime requested by the card. Before receiving the next character, the card requires a delay of
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at least (12+N) etu from the start leading edge of the previous character. No extra guardtme is used to send
characters from the card to the interface device.
The default values of these parameters are:
F = 372 ; D = 1 ; I = 50 ; P = 5 ; N = 0
- Integer values in global interface bytes
----------------------------------------
The global interface bytes, TA1, TB1, TC1, TB2 code integer values FI, DI II, PI1, N, PI2 which are either equal
to or used to compute the values of the parameters F, D, I, P, N presented above.
TA1 codes FI over the most significant half byte (b8 to b5) and DI over the least significant half byte (b4 to b1).
TB1 codes II over the bits b7 and b6, and PI1 over the 5 least significant bits b5 to b1. The most significant bit
b8 equals to 0.
NOTE : The interface device may ignore the bit b8 of TB1.
TC1 codes N over the eight bits (b8 to b1).
TB2 codes PI2 over the eight bits (b8 to b1).
Table 6: Clock rate conversion factor F
-------
----------------------------------------------------------------------
FI | 0000 0001 0010 0011 0100 0101 0110 0111
--------------+-------------------------------------------------------
F | Internal clk 372 558 744 1116 1488 1860 RFU
--------------+-------------------------------------------------------
fs (max) MHz | - 5 6 8 12 16 20 -
----------------------------------------------------------------------
---------------------------------------------------------------
FI | 1000 1001 1010 1011 1100 1101 1110 1111
--------------+------------------------------------------------
F | RFU 512 768 1024 1536 2048 RFU RFU
--------------+------------------------------------------------
fs (max) MHz | - 5 7.5 10 15 20 - -
---------------------------------------------------------------
RFU : Reserved for Future Use
Table 7: Bit rate afjustment factor D
-------
-------------------------------------------------------
DI | 0000 0001 0010 0011 0100 0101 0110 0111
------+------------------------------------------------
D | RFU 1 2 4 8 16 RFU RFU
-------------------------------------------------------
-------------------------------------------------------
DI | 1000 1001 1010 1011 1100 1101 1110 1111
------+------------------------------------------------
D | RFU RFU 1/2 1/4 1/8 1/16 1/32 1/64
-------------------------------------------------------
RFU : Reserved for Future Use
- Programming voltage factor P
----------------------------
PI1 from 5 to 25 gives the value of P in volts. PI1=0 indicates that VPP is connected in the card which generates
an internal programming voltage from VCC. Other values of PI1 are reserved for future use.
When PI2 is present, the indication of PI1 should be ignores. PI2 from 50 to 250 gives the value of P in 0.1V.
Other values of PI2 are reserved for future use.
Table 8 : Maximum programming current factor I
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-------
-------------------------------
II | 00 01 10 11
-----+-------------------------
I | 25 50 100 RFU
-------------------------------
- Extra guardtime N
-----------------
N codes directly the extra guard time, from 0 to 254 etu. N=255 indicates that the minimum delay between the
start edges of two consecutives characters is reduced to 11 etu.
b - Answer to Reset in synchronous transmission
-------------------------------------------
* Clock frequency and bit rate
""""""""""""""""""""""""""""
There is a linear relationship between the bit rate on the I/O line and the clock frequency provided by the clock
